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1 ltc1068 series clock-tunable, quad second order, filter building blocks s f ea t u re n four identical 2nd order filter sections in an ssop package n 2nd order section center freque ncy error: 0.3% typical and 0.8% maximum n low noise per 2nd order section, q 5: LTC1068-200 50 m v rms , ltc1068 50 m v rms ltc1068-50 75 m v rms , ltc1068-25 90 m v rms n low power supply current: 4.5ma, single 5v, ltc1068-50 n operation with 5v power supply, single 5v supply or single 3.3v supply the ltc ? 1068 product family consists of four monolithic clock-tunable filter building blocks. each product contains four matched, low noise, high accuracy 2nd order switched- capacitor filter sections. an external clock tunes the center frequency of each 2nd order filter section. the ltc1068 products differ only in their clock-to-center frequency ratio. the clock-to-center frequency ratio is set to 200:1 (LTC1068-200), 100:1 (ltc1068), 50:1 (ltc1068-50) or 25:1 (ltc1068-25). external resistors can modify the clock-to-center frequency ratio. high performance, quad 2nd order, dual 4th order or 8th order filters can be designed with an ltc1068 family product. designing filters with an ltc1068 product is fully supported by filtercad tm filter design software for windows ? . the ltc1068 products are available in a 28-pin ssop surface mount package. a customized version of an ltc1068 family product can be obtained in a 16-lead so package with internal thin-film resistors. please contact ltc marketing for details. d u escriptio filtercad is a trademark of linear technology corporation. windows is a registered trademark of microsoft corporation. , ltc and lt are registered trademarks of linear technology corporation. u s a o pp l ic at i u a o pp l ic at i ty p i ca l dual, matched, 4th order butterworth lowpass filters, clock-tunable up to 200khz f C 3db = f clk /25, 4th order filter noise = 60 m v rms inv b hpb/nb bpb lpb sb nc agnd v + nc sa lpa bpa hpa/na inva 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 inv c hpc/nc bpc lpc sc v nc clk nc sd lpd bpd hpd/nd invd ltc1068-25 r31 20k r33 20k r23 14k r13 20k 0.1 m f r21 14k r22 20k r12 14k r32 10k r34 10k r24 20k r14 14k r11 20k v in1 v in2 5v 1 m f v out1 v out2 1068 ta20a ?v f clk = (25)(f ?3db) relative frequency [f in /(f ?3db)] 0.1 gain (db) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 110 1068 ta20b 10 0 gain vs frequency n lowpass or highpass filters: LTC1068-200, 0.5hz to 25khz; ltc1068, 1hz to 50khz; ltc1068-50, 2hz to 50khz; ltc1068-25, 4hz to 200khz n bandpass or bandreject (notch) filters: LTC1068-200, 0.5hz to 15khz; ltc1068, 1hz to 30khz; ltc1068-50, 2hz to 30khz; ltc1068-25, 4hz to 140khz
2 ltc1068 series a u g w a w u w a r b s o lu t exi t i s total supply voltage (v + to v C ) .............................. 12v power dissipation ............................................. 500mw input voltage at any pin .... v C C 0.3v v in v + + 0.3v storage temperature range ................. C 65 c to 150 c operating temperature range ltc1068c ................................................ 0 c to 70 c ltc1068i ........................................... C 40 c to 85 c lead temperature (soldering, 10 sec).................. 300 c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view g package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 inv b hpb/nb bpb lpb sb nc agnd v + nc sa lpa bpa hpa/na inv a inv c hpc/nc bpc lpc sc v nc clk nc sd lpd bpd hpd/nd inv d consult factory for military grade parts. t jmax = 110 c, q ja = 95 c/w ltc1068cn ltc1068in 1 2 3 4 5 6 7 8 9 10 11 12 top view 24 23 22 21 20 19 18 17 16 15 14 13 inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a inv c hpc/nc bpc lpc sc v clk sd lpd bpd hpd/nd inv d n package 24-lead pdip t jmax = 110 c, q ja = 65 c/w order part number order part number ltc1068cg ltc1068cg-200 ltc1068cg-50 ltc1068cg-25 ltc1068ig ltc1068ig-200 ltc1068ig-50 ltc1068ig-25 wu u package / o rder i for atio electrical characteristics ltc1068 (internal op amps) v s = 5v, t a = 25 v, unless otherwise noted. parameter conditions min typ max units operating supply voltage range 3.14 5.5 v voltage swings v s = 3.14v, r l = 5k (note 2) l 1.2 1.6 v p-p v s = 4.75v, r l = 5k (note 3) l 2.6 3.2 v p-p v s = 5v, r l = 5k l 3.4 4.1 v output short-circuit current (source/sink) v s = 4.75v 17/6 ma v s = 5v 20/15 ma dc open-loop gain r l = 5k 85 db gbw product v s = 5v 6 mhz slew rate v s = 5v 10 v/ m s analog ground voltage (note 4) v s = 5v, voltage at agnd 2.5v 2% v (note 1)
3 ltc1068 series electrical characteristics ltc1068 (complete filter) v s = 5v, t a = 25 v, unless otherwise noted. parameter conditions min typ max units clock-to-center frequency ratio (note 5) v s = 4.75v, f clk = 1mhz, mode 1 (note 3), 100 0.3 100 0.8 % f o = 10khz, q = 5, v in = 0.5v rms , l 100 0.9 % r1 = r3 = 49.9k, r2 = 10k v s = 5v, f clk = 1mhz, mode 1, 100 0.3 100 0.8 % f o = 10khz, q = 5, v in = 1v rms , l 100 0.9 % r1 = r3 = 49.9k, r2 = 10k clock-to-center frequency ratio, v s = 4.75v, f clk = 1mhz, q = 5 (note 3) l 0.25 0.9 % side-to-side matching (note 5) v s = 5v, f clk = 1mhz, q = 5 l 0.25 0.9 % q accuracy (note 5) v s = 4.75v, f clk = 1mhz, q = 5 (note 3) l 1 3% v s = 5v, f clk = 1mhz, q = 5 l 1 3% f o temperature coefficient 1 ppm/ c q temperature coefficient 5 ppm/ c dc offset voltage (note 5) v s = 5v, f clk = 1mhz, v os1 l 0 15 mv (see table 1) (dc offset of input inverter) v s = 5v, f clk = 1mhz, v os2 l 2 25 mv (dc offset of first integrator) v s = 5v, f clk = 1mhz, v os3 l 5 40 mv (dc offset of second integrator) clock feedthrough v s = 5v, f clk = 1mhz 0.1 mv rms max clock frequency (note 6) v s = 5v, q 2.0, mode 1 5.6 mhz power supply current v s = 3.14v, f clk = 1mhz (note 2) l 3.5 8 ma v s = 4.75v, f clk = 1mhz (note 3) l 6.5 11 ma v s = 5v, f clk = 1mhz l 9.5 15 ma parameter conditions min typ max units clock-to-center frequency ratio (note 5) v s = 4.75v, f clk = 1mhz, mode 1 (note 3), 200 0.3 200 0.8 % f o = 5khz, q = 5, v in = 0.5v rms , l 200 0.9 % r1 = r3 = 49.9k, r2 = 10k v s = 5v, f clk = 1mhz, mode 1, 200 0.3 200 0.8 % f o = 5hz, q = 5, v in = 1v rms , l 200 0.9 % r1 = r3 = 49.9k, r2 = 10k LTC1068-200 (complete filter) v s = 5v, t a = 25 v, unless otherwise noted. parameter conditions min typ max units operating supply voltage range 3.14 5.5 v voltage swings v s = 3.14v, r l = 5k (note 2) l 1.2 1.6 v p-p v s = 4.75v, r l = 5k (note 3) l 2.6 3.2 v p-p v s = 5v, r l = 5k l 3.4 4.1 v output short-circuit current (source/sink) v s = 4.75v 17/6 ma v s = 5v 20/15 ma dc open-loop gain r l = 5k 85 db gbw product v s = 5v 6 mhz slew rate v s = 5v 10 v/ m s analog ground voltage (note 4) v s = 5v, voltage at agnd 2.5v 2% v LTC1068-200 (internal op amps) v s = 5v, t a = 25 v, unless otherwise noted.
4 ltc1068 series electrical characteristics LTC1068-200 (complete filter) v s = 5v, t a = 25 v , unless otherwise noted. parameter conditions min typ max units clock-to-center frequency ratio, v s = 4.75v, f clk = 1mhz, q = 5 (note 3) l 0.25 0.9 % side-to-side matching (note 5) v s = 5v, f clk = 1mhz, q = 5 l 0.25 0.9 % q accuracy (note 5) v s = 4.75v, f clk = 1mhz, q = 5 (note 3) l 1 3% v s = 5v, f clk = 1mhz, q = 5 l 1 3% f o temperature coefficient 1 ppm/ c q temperature coefficient 5 ppm/ c dc offset voltage (note 5) v s = 5v, f clk = 1mhz, v os1 l 0 15 mv (see table 1) (dc offset of input inverter) v s = 5v, f clk = 1mhz, v os2 l 2 25 mv (dc offset of first integrator) v s = 5v, f clk = 1mhz, v os3 l 5 40 mv (dc offset of second integrator) clock feedthrough v s = 5v, f clk = 1mhz 0.1 mv rms max clock frequency (note 6) v s = 5v, q 2.0, mode 1 5.6 mhz power supply current v s = 3.14v, f clk = 1mhz (note 2) l 3.5 8 ma v s = 4.75v, f clk = 1mhz (note 3) l 6.5 11 ma v s = 5v, f clk = 1mhz l 9.5 15 ma parameter conditions min typ max units clock-to-center frequency ratio (note 5) v s = 3.14v, f clk = 250khz, mode 1 (note 2), 50 0.3 50 0.8 % f o = 5khz, q = 5, v in = 0.34v rms , l 50 0.9 % r1 = r3 = 49.9k, r2 = 10k v s = 5v, f clk = 500khz, mode 1, 50 0.3 50 0.8 % f o = 10khz, q = 5, v in = 1v rms , l 50 0.9 % r1 = r3 = 49.9k, r2 = 10k clock-to-center frequency ratio, v s = 3.14v, f clk = 250khz, q = 5 (note 2) l 0.25 0.9 % side-to-side matching (note 5) v s = 5v, f clk = 500khz, q = 5 l 0.25 0.9 % q accuracy (note 5) v s = 3.14v, f clk = 250khz, q = 5 (note 2) l 1 3% v s = 5v, f clk = 500khz, q = 5 l 1 3% ltc1068-50 (complete filter) v s = 5v, t a = 25 v, unless otherwise noted. parameter conditions min typ max units operating supply voltage range 3.14 5.5 v voltage swings v s = 3.14v, r l = 5k (note 2) l 1.2 1.8 v p-p v s = 4.75v, r l = 5k (note 3) l 2.6 3.6 v p-p v s = 5v, r l = 5k l 3.4 4.1 v output short-circuit current (source/sink) v s = 3.14v 17/6 ma v s = 5v 20/15 ma dc open-loop gain r l = 5k 85 db gbw product v s = 5v 4 mhz slew rate v s = 5v 7 v/ m s analog ground voltage (note 4) v s = 5v, voltage at agnd 2.175v 2% v ltc1068-50 (internal op amps) v s = 5v, t a = 25 v, unless otherwise noted.
5 ltc1068 series electrical characteristics ltc1068-50 (complete filter) v s = 5v, t a = 25 v , unless otherwise noted. parameter conditions min typ max units f o temperature coefficient 1 ppm/ c q temperature coefficient 5 ppm/ c dc offset voltage (note 5) v s = 5v, f clk = 500khz, v os1 l 0 15 mv (see table 1) (dc offset of input inverter) v s = 5v, f clk = 500khz, v os2 l C2 25 mv (dc offset of first integrator) v s = 5v, f clk = 500khz, v os3 l C5 40 mv (dc offset of second integrator) clock feedthrough v s = 5v, f clk = 500khz 0.16 mv rms max clock frequency (note 6) v s = 5v, q 1.6, mode 1 3.4 mhz power supply current v s = 3.14v, f clk = 250khz (note 2) l 3.0 5 ma v s = 4.75v, f clk = 250khz (note 3) l 4.3 8 ma v s = 5v, f clk = 500khz l 6.0 11 ma ltc1068-25 (internal op amps) v s = 5v, t a = 25 v , unless otherwise noted. parameter conditions min typ max units operating supply voltage range 3.14 5.5 v voltage swings v s = 3.14v, r l = 5k (note 2) l 1.2 1.6 v p-p v s = 4.75v, r l = 5k (note 3) l 2.6 3.4 v p-p v s = 5v, r l = 5k l 3.4 4.1 v output short-circuit current (source/sink) v s = 4.75v 17/6 ma v s = 5v 20/15 ma dc open-loop gain r l = 5k 85 db gbw product v s = 5v 6 mhz slew rate v s = 5v 10 v/ m s analog ground voltage (note 4) v s = 5v, voltage at agnd 2.5v 2% v ltc1068-25 (complete filter) v s = 5v, t a = 25 v, unless otherwise noted. parameter conditions min typ max units clock-to-center frequency ratio (note 5) v s = 4.75v, f clk = 500khz, mode 1 (note 3), 25 0.3 25 0.8 % f o = 20khz, q = 5, v in = 0.5v rms , l 25 0.9 % r1 = r3 = 49.9k, r2 = 10k v s = 5v, f clk = 1mhz, mode 1, 25 0.3 25 0.8 % f o = 40khz, q = 5, v in = 1v rms , l 25 0.9 % r1 = r3 = 49.9k, r2 = 10k clock-to-center frequency ratio, v s = 4.75v, f clk = 500khz, q = 5 (note 3) l 0.25 0.9 % side-to-side matching (note 5) v s = 5v, f clk = 1mhz, q = 5 l 0.25 0.9 % q accuracy (note 5) v s = 4.75v, f clk = 500khz, q = 5 (note 3) l 1 3% v s = 5v, f clk = 1mhz, q = 5 l 1 3% f o temperature coefficient 1 ppm/ c q temperature coefficient 5 ppm/ c
6 ltc1068 series electrical characteristics table 1. output dc offsets one 2nd order section mode v osn v osbp v oslp 1v os1 [(1/q) + 1 + ||holp||] C v os3 /q v os3 v osn C v os2 1b v os1 [(1/q) + 1 + r2/r1] C v os3 /q v os3 ~(v osn C v os2 )(1 + r5/r6) 2[v os1 (1 + r2/r1 + r2/r3 + r2/r4) C v os3 (r2/r3)x v os3 v osn C v os2 [r4/(r2 + r4)] + v os2 [r2/(r2 + r4)] 3v os2 v os3 v os1 [1 + r4/r1 + r4/r2 + r4/r3] C v os2 (r4/r2) C v os3 (r4/r3) ltc1068 maximum q vs center frequency (modes 1, 1b, 2) center frequency, f o (khz) 0 abc 0 maximum q 5 15 20 25 50 35 20 40 50 1068 g01 10 40 45 30 10 30 60 70 a. v s = 3.3v, f clk(max) = 1.5mhz b. v s = 5v, f clk(max) = 3.4mhz c. v s = 5v, f clk(max) = 5.6mhz (for mode 2 r4 3 10r2) LTC1068-200 maximum q vs center frequency (modes 1, 1b, 2) center frequency, f o (khz) 0 a bc 55 50 45 40 35 30 25 20 15 10 5 0 typical maximum q 8 16 20 24 1068 g03 4 12 28 32 a: v s = 3.3v, f clk(max) = 1.2mhz b: v s = 5v, f clk(max) = 3.2mhz c: v s = 5v, f clk(max) = 6.1mhz (for mode 2, r4 3 10r2) typical perfor m a n ce characteristics u w ltc1068 maximum q vs center frequency (modes 2, 3) center frequency, f o (khz) 0 ab c 0 maximum q 5 15 20 25 50 35 20 40 50 1068 g02 10 40 45 30 10 30 60 a. v s = 3.3v, f clk(max) = 1mhz b. v s = 5v, f clk(max) = 3mhz c. v s = 5v, f clk(max) = 5mhz (for mode 2 r4 < 10r2) ltc1068-25 (complete filter) v s = 5v, t a = 25 v , unless otherwise noted. parameter conditions min typ max units dc offset voltage (note 5) v s = 5v, f clk = 1mhz, v os1 l 0 15 mv (see table 1) (dc offset of input inverter) v s = 5v, f clk = 1mhz, v os2 l C2 25 mv (dc offset of first integrator) v s = 5v, f clk = 1mhz, v os3 l C5 40 mv (dc offset of second integrator) clock feedthrough v s = 5v, f clk = 1mhz 0.25 mv rms max clock frequency (note 6) v s = 5v, q 1.6, mode 1 5.6 mhz power supply current v s = 3.14v, f clk = 1mhz (note 2) l 3.5 8 ma v s = 4.75v, f clk = 1mhz (note 3) l 6.5 11 ma v s = 5v, f clk = 1mhz l 9.5 15 ma the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: production testing for single 3.14v supply is achieved by using the equivalent dual supplies of 1.57v. note 3: production testing for single 4.75v supply is achieved by using the equivalent dual supplies of 2.375v. note 4: pin 7 (agnd) is the internal analog ground of the device. for single supply applications this pin should be bypassed with a 1 m f capacitor. the biasing voltage of agnd is set with an internal resistive divider from pin 8 to pin 23 (see block diagram). note 5: side d is guaranteed by design. note 6: see typical performance characteristics.
7 ltc1068 series typical perfor m a n ce characteristics u w ltc1068-50 maximum q vs center frequency (modes 2, 3) center frequency, f o (khz) 0 a b c 55 50 45 40 35 30 25 20 15 10 5 0 typical maximum q 8 16 20 24 1068 g06 4 12 28 32 a: v s = 3.3v, f clk(max) = 1.1mhz b: v s = 5v, f clk(max) = 2.1mhz c: v s = 5v, f clk(max) = 3.6mhz (for mode 2, r4 < 10r2) ltc1068 center frequency variation vs clock frequency clock frequency (mhz) 0.75 1.25 1.75 2.25 2.75 3.25 3.75 0.6 center frequency variation (% error) 0.4 0 0.2 0.4 1.2 1068 g09 0.2 4.25 0.6 0.8 1.0 mode 3 mode 1 v s = 5v q = 5, reference center frequency with f clk = 0.75mhz clock frequency (mhz) 0.75 1.25 1.75 2.25 2.75 3.25 3.75 0.25 center frequency variation (% error) 0.20 0.10 0.05 0 0.20 1068 g10 0.15 4.25 0.05 0.10 0.15 mode 3 mode 1 v s = 5v q = 5, reference center frequency with f clk = 0.75mhz LTC1068-200 center frequency variation vs clock frequency ltc1068-25 center frequency variation vs clock frequency clock frequency (mhz) 0.5 0 battery voltage (v) 0.3 0.8 1.3 1.8 1.0 1.5 2.0 2.5 1068 g12 3.0 3.5 mode 1 mode 3 v s = 5v q = 5, reference center frequency with f clk = 0.5mhz LTC1068-200 maximum q vs center frequency (modes 2, 3) center frequency, f o (khz) 0 a bc 55 50 45 40 35 30 25 20 15 10 5 0 typical maximum q 8 16 20 24 1068 g04 4 12 28 32 a: v s = 3.3v, f clk(max) = 1.2mhz b: v s = 5v, f clk(max) = 3.2mhz c: v s = 5v, f clk(max) = 6.1mhz (for mode 2, r4 < 10r2) ltc1068-25 maximum q vs center frequency (modes 1, 1b, 2) center frequency, f o (khz) 0 a b c typical maximum q 55 50 45 40 35 30 25 20 15 10 5 0 64 128 160 1068 g07 32 96 192 224 a: v s = 3.3v, f clk(max) = 1.2mhz b: v s = 5v, f clk(max) = 3.4mhz c: v s = 5v, f clk(max) = 6.1mhz (for mode 2, r4 3 10r2) ltc1068-50 center frequency variation vs clock frequency clock frequency (mhz) 0.5 0.2 center frequency variation (% error) 0.1 0 0.1 0.2 0.4 0.75 1.0 1.25 1.5 1068 g11 1.75 2.0 0.3 mode 1 mode 3 v s = 5v q = 5, reference center frequency with f clk = 0.5mhz ltc1068-50 maximum q vs center frequency (modes 1, 1b, 2) center frequency, f o (khz) 0 a b c 55 50 45 40 35 30 25 20 15 10 5 0 typical maximum q 8 16 20 24 1068 g05 4 12 28 32 a: v s = 3.3v, f clk(max) = 1.1mhz b: v s = 5v, f clk(max) = 2.1mhz c: v s = 5v, f clk(max) = 3.6mhz (for mode 2, r4 3 10r2) ltc1068-25 maximum q vs center frequency (modes 2, 3) frequency, f o (khz) 0 a b c typical maximum q 55 50 45 40 35 30 25 20 15 10 5 0 64 128 160 1068 g08 32 96 192 224 a: v s = 3.3v, f clk(max) = 1mhz b: v s = 5v, f clk(max) = 3mhz c: v s = 5v, f clk(max) = 5mhz (for mode 2, r4 < 10r2)
8 ltc1068 series typical perfor m a n ce characteristics u w ltc1068/LTC1068-200 noise vs q q 0 0 noise ( m v rms ) 50 100 150 200 10 20 30 5v 5v 3.3v 40 1068 g13 250 300 515 25 35 q 0 0 noise ( m v rms ) 50 100 150 200 10 20 30 5v 3.3v 40 1068 g15 250 300 515 25 35 5v ltc1068-25 noise vs q q 0 0 noise ( m v rms ) 50 100 150 200 10 20 30 5v 3.3v 40 1068 g14 250 300 515 25 35 5v ltc1068-50 noise vs q r2/r4 ratio 0.2 0 relative noise increase (reference noise when r2/r4 = 1) 1.1 1.3 1.4 1.5 2.0 1.7 0.4 0.6 0.7 1068 g16 1.2 1.8 1.9 1.6 0.3 0.5 0.8 0.9 1.0 noise increase vs r2/r4 ratio (mode 3) noise increase vs r5/r6 ratio (mode 1b) r5/r6 ratio 0 0 relative noise increase (reference noise when r5/r6 = 0.02) 1.1 1.3 1.4 1.5 2.0 1.7 1.0 2.0 2.5 1068 g17 1.2 1.8 1.9 1.6 0.5 1.5 3.0 3.5 ltc1068/LTC1068-200/ ltc1068-25 power supply current vs power supply total power supply (v) 3 power supply current (ma) 8.5 9.5 10.5 68 lt1027 ?tpcxx 7.5 6.5 45 7910 5.5 4.5 25 c 70 c ?0 c total power supply (v) 3 power supply current (ma) 6 7 8 68 1068 g19 5 4 45 7910 3 2 25 c 70 c ?0 c ltc1068-50 power supply current vs power supply
9 ltc1068 series pi n fu n ctio n s uuu power supply pins the v + and v C pins should each be bypassed with a 0.1 m f capacitor to an adequate analog ground. the filters power supplies should be isolated from other digital or high voltage analog supplies. a low noise linear supply is recommended. using a switching power supply will lower the signal-to-noise ratio of the filter. figures 1 and 2 show typical connections for dual and single supply operation. analog ground pin the filters performance depends on the quality of the analog signal ground. for either dual or single supply operation, an analog ground plane surrounding the pack- age is recommended. the analog ground plane should be connected to any digital ground at a single point. for single supply operation, agnd should be bypassed to the analog ground plane with at least a 0.47 m f capacitor (figure 2). two internal resistors bias the analog ground pin. for the ltc1068, LTC1068-200 and ltc1068-25, the voltage at the analog ground pin (agnd) for single supply is 0.5 v + and for the ltc1068-50 it is 0.435 v + . clock input pin any ttl or cmos clock source with a square-wave output and 50% duty cycle ( 10%) is an adequate clock source for the device. the power supply for the clock source should not be the filters power supply. the analog ground for the filter should be connected to clocks ground at a single point only. table 2 shows the clocks low and high level threshold values for dual or single supply operation. table 2. clock source high and low threshold levels power supply high level low level dual supply = 5v 3 1.53v 0.53v single supply = 5v 3 1.53v 0.53v single supply = 3.3v 3 1.20v 0.53v a pulsed generator can be used as a clock source provided the high level on time is at least 25% of the pulse period. sine waves are not recommended for clock input frequen- cies less than 100khz, since excessively slow clock rise or fall times generate internal clock jitter (maximum clock rise or fall time 1 m s). the clock signal should be routed from the right side of the ic package and perpendicular to it to avoid coupling to any input or output analog signal figure 1. dual supply ground plane connections figure 2. single supply ground plane connections 0.1 m f v 1068 f01 200 w digital ground v + ltc1068 clock source 0.1 m f analog ground plane 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 star system ground 1068 f02 200 w digital ground for mode 3, the s node should be tied to pin 7 (agnd) v + ltc1068 r a r b clock source 0.1 m f v agnd 0.47 m f (1 m f for stopband frequencies 1khz) analog ground plane 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 star system ground device ltc1068 LTC1068-200 ltc1068-25 ltc1068-50 r a 10k 11.3k r b 10k 8.6k
10 ltc1068 series pi n fu n ctio n s uuu path. a 200 w resistor between clock source and pin 11 will slow down the rise and fall times of the clock to further reduce charge coupling (figures 1 and 2). output pins each 2nd order section of an ltc1068 device has three outputs that typically source 17ma and sink 6ma. driving coaxial cables or resistive loads less than 20k will degrade the total harmonic distortion performance of any filter design. when evaluating the distortion or noise perfor- mance of a particular filter design implemented with a ltc1068 device, the final output of the filter should be buffered with a wideband, noninverting high slew rate amplifier (figure 3). inverting input pins these pins are the inverting inputs of internal op amps and are susceptible to stray capacitive coupling from low impedance signal outputs and power supply lines. + lt 1354 1k 1068 f03 r a * r b * v + (8) clk (21) v (23) nc (6) nc (9) nc (20) nc (22) agnd (7) 1068 bd + + + + + + + hpc/nc (27) bpc (26) lpc (25) hpb/nb (2) bpb (3) lpb (4) *the ratio r a /r b varies 2% bpa (12) lpa (11) inv a (14) agnd (7) inv c (28) hpa/na (13) + s sa (10) + + + + inv d (15) inv b (1) hpd/nd (16) s sb (5) s sc (24) s sd (19) + + + bpd (17) + lpd (18) pin 28-lead ssop package device ltc1068 LTC1068-200 ltc1068-25 ltc1068-50 r a 10k 11.3k r b 10k 8.6k block diagra m w in a printed circuit layout any signal trace, clock source trace or power supply trace should be at least 0.1 inches away from any inverting input pins summing input pins these are voltage input pins. if used, they should be driven with a source impedance below 5k. when they are not used, they should be tied to the analog ground pin. the summing pin connections determine the circuit topol- ogy (mode) of each 2nd order section. please refer to modes of operation. figure 3. wideband buffer
11 ltc1068 series m odes of operatio n u w linear technologys universal switched-capacitor filters are designed for a fixed internal, nominal f clk /f o ratio. the f clk /f o ratio is 100 for the ltc1068, 200 for the ltc1068- 200, 50 for the ltc1068-50 and 25 for the ltc1068-25. filter designs often require the f clk /f o ratio of each section to be different from the nominal ratio and in most cases different from each other. ratios other than the nominal value are possible with external resistors. operating modes use external resistors, connected in different arrange- ments to realize different f clk /f o ratios. by choosing the proper mode, the f clk /f o ratio can be increased or de- creased from the parts nominal ratio. the choice of operating mode also effects the transfer function at the hp/n pins. the lp and bp pins always give the lowpass and bandpass transfer functions respectively, regardless of the mode utilized. the hp/n pins have a different transfer function depending on the mode used. mode 1 yields a notch transfer function. mode 3 yields a highpass transfer function. mode 2 yields a highpass notch transfer function (i.e., a highpass with a stopband notch). more complex transfer functions, such as lowpass notch, allpass or complex zeros, are achieved by summing two or more of the lp, bp or hp/n outputs. this is illustrated in sections mode 2n and mode 3a. choosing the proper mode(s) for a particular application is not trivial and involves much more than just adjusting the f clk /f o ratio. listed here are four of the nearly twenty modes available. to make the design process simpler and quicker, linear technology has developed the filtercad for widows design software. filtercad is an easy-to-use, powerful and interactive filter design program. the de- signer can enter a few filter specifications and the program produces a full schematic. filtercad allows the designer to concentrate on the filters transfer function and not get bogged down in the details of the design. alternatively, those who have experience with the linear technology family of parts can control all of the details themselves. for a complete listing of all the operating modes, consult the appendices of the filtercad manual or the help files in filtercad. filtercad can be obtained free of charge on the linear technology web site (www.linear-tech.com) or you can order the filtercad cd-rom by contacting linear technology marketing. mode 1 in mode 1, the ratio of the external clock frequency to the center frequency of each 2nd order section is internally fixed at the parts nominal ratio. figure 4 illustrates mode 1 providing 2nd order notch, lowpass and bandpass outputs. mode 1 can be used to make high order butter- worth lowpass filters; it can also be used to make low q notches and for cascading 2nd order bandpass functions tuned at the same center frequency. mode 1 is faster than mode 3. please refer to the operating limits paragraph under appli- cations information for a guide to the use of capacitor c c . mode 1b mode 1b is derived from mode 1. in mode 1b (figure 5) two additional resistors r5 and r6 are added to lower the amount of voltage fed back from the lowpass output into the input of the sa (or sb) switched-capacitor summer. this allows the filters clock-to-center frequency ratio to be adjusted beyond the parts nominal ratio. mode 1b maintains the speed advantages of mode 1 and should be considered an optimum mode for high q designs with f clk to f cutoff (or f center ) ratios greater than the parts nominal ratio. the parallel combination of r5 and r6 should be kept below 5k. please refer to the operating limits paragraph under appli- cations information for a guide to the use of capacitor c c . figure 4. mode 1, 2nd order filter providing notch, bandpass and lowpass outputs + s agnd r1 n bp lp v in 1068 f04 + s r2 r3 c c f o = ; f n = f o q = ; h on = ? ; h obp = ? h olp = h on r2 r1 r3 r1 r3 r2 f clk ratio device ltc1068 LTC1068-200 ltc1068-50 ltc1068-25 ratio 100 200 50 25
12 ltc1068 series m odes of operatio n u w + s agnd r1 hp bp lp v in 1068 f06 + s 1/4 ltc1068 r2 r3 c c r4 f o = f clk ratio r3 r2 ? r2 r4 r3 (ratio)(0.32)(r4) ( ) 1 1 ? r3 (ratio)(0.32)(r4) ( ) 1 1 ? ( ) ? r2 r4 h ohp = ? ; h obp = ? r2 r1 r3 r1 r4 r1 ; h olp = ? ; q = 1.005 device ltc1068 LTC1068-200 ltc1068-50 ltc1068-25 ratio 100 200 50 25 figure 7. mode 2, 2nd order filter providing highpass notch, bandpass and lowpass outputs + s agnd r1 hpn bp lp v in 1068 f07 + s r2 r3 c c r4 f o = ; f n = f clk ratio f clk ratio ? r2 r4 1 + q = 1.005 r3 r2 ( ) ? r2 r4 1 + r3 (ratio)(0.32)(r4) ( ) 1 1 r3 (ratio)(0.32)(r4) ( ) 1 1? h ohpn = ? (ac gain, f >> f o ); h ohpn = r2 r1 r2 r1 r2 r1 1 r2 r4 1 + ( ) 1 r2 r4 1 + ( ) (dc gain) h obp = r3 r1 ; h olp = ? device ltc1068 LTC1068-200 ltc1068-50 ltc1068-25 ratio 100 200 50 25 figure 6. mode 3, 2nd order section providing highpass, bandpass and lowpass outputs + s agnd r1 n bp lp v in 1068 f05 + s r2 r3 c c r5 r6 f o = ; f n = f o q = ; h on = ? ; h obp = ? h olp = ? r2 r1 r3 r1 r3 r2 f clk ratio ? r6 (r6 + r5) r2 r1 r6 + r5 r6 ? r6 (r6 + r5) () device ltc1068 LTC1068-200 ltc1068-50 ltc1068-25 ratio 100 200 50 25 figure 5. mode 1b, 2nd order filter providing notch, bandpass and lowpass outputs mode 3 in mode 3, the ratio of the external clock frequency to the center frequency of each 2nd order section can be ad- justed above or below the parts nominal ratio. figure 6 illustrates mode 3, the classical state variable configura- tion, providing highpass, bandpass and lowpass 2nd order filter functions. mode 3 is slower than mode 1. mode 3 can be used to make high order all-pole bandpass, lowpass and highpass filters. please refer to the operating limits paragraph under appli- cations information for a guide to the use of capacitor c c . mode 2 mode 2 is a combination of mode 1 and mode 3, shown in figure 7. with mode 2, the clock-to-center frequency ratio, f clk /f o , is always less than the parts nominal ratio. the advantage of mode 2 is that it provides less sensitivity to resistor tolerances than does mode 3. mode 2 has a highpass notch output where the notch frequency de- pends solely on the clock frequency and is therefore less than the center frequency, f o . please refer to the operating limits paragraph under appli- cations information for a guide to the use of capacitor c c .
13 ltc1068 series applicatio n s i n for m atio n wu u u mine the operating signal-to-noise ratio. most of its fre- quency contents lie within the filter passband and cannot be reduced with post filtering. for a notch filter the noise of the filter is centered at the notch frequency. the total wideband noise ( m v rms ) is nearly independent of the value of the clock. the clock feedthrough specifica- tions are not part of the wideband noise. for a specific filter design, the total noise depends on the q of each section and the cascade sequence. please refer to the noise vs q graphs under the typical performance characteristics. aliasing aliasing is an inherent phenomenon of switched-capacitor filters and occurs when the frequency of the input signals that produce the strongest aliased components have a frequency, f in , such as (f sampling C f in ) that falls into the filters passband. for an ltc1068 device the sampling frequency is twice f clk . if the input signal spectrum is not band-limited, aliasing may occur. demonstration circuit 104 dc104 is a surface mount printed circuit board for the evaluation of linear technologys ltc1068 product fam- ily in a 28-lead ssop package. the ltc1068 product family consists of four monolithic clock-tunable filter building blocks. demo board 104 is available in four assembled versions: assembly 104-a features the low noise ltc1068cg (clock- to-center frequency ratio = 100), assembly 104-b features the low noise ltc1068cg-200 (clock-to-center frequency ratio = 200), assembly 104-c features the high frequency ltc1068cg-25 (clock-to-center frequency ratio = 25) and assembly 104-d features the low power ltc1068cg-50 (clock-to-center frequency ratio = 50). all dc104 boards are assembled with input, output and power supply test terminals, a 28-lead ssop filter device (ltc1068cg series), a dual op amp in an so-8 for input or output buffers and decoupling capacitors for the filter and op amps. the filter and dual op amps share the power operating limits the maximum q vs center frequency (f o ) graphs, under typical performance characteristics, define an upper limit of operating q for each ltc1068 device 2nd order section. these graphs indicate the power supply, f o and q value conditions under which a filter implemented with an ltc1068 device will remain stable when operated at temperatures of 70 c or less. for a 2nd order section, a bandpass gain error of 3db or less is arbitrarily defined as a condition for stability. when the passband gain error begins to exceed 1db, the use of capacitor c c will reduce the gain error (capacitor c c is connected from the lowpass node to the inverting node of a 2nd order section). please refer to figures 4 through 7. the value of c c can be best determined experimentally, and as a guide it should be about 5pf for each 1db of gain error and not to exceed 15pf. when operating an ltc1068 device near the limits defined by the maximum q vs frequency graphs, passband gain variations of 2db or more should be expected. clock feedthrough clock feedthrough is defined as the rms value of the clock frequency and its harmonics that are present at the filters output pins. the clock feedthrough is tested with the filters input grounded and depends on pc board layout and on the value of the power supplies. with proper layout techniques, the typical values of clock feedthrough are listed under electrical characteristics. any parasitic switching transients during the rising and falling edges of the incoming clock are not part of the clock feedthrough specifications. switching transients have fre- quency contents much higher than the applied clock; their amplitude strongly depends on scope probing techniques as well as grounding and power supply bypassing. the clock feedthrough, can be greatly reduced by adding a simple rc lowpass network at the final filter output. this rc will completely eliminate any switching transients. wideband noise the wideband noise of the filter is the total rms value of the devices noise spectral density and is used to deter-
14 ltc1068 series supply inputs to the board. jumpers jpa to jpd on the board configure the filters second order circuit modes, jumper jp1 configures the filter for dual or single supply operation and jumpers jp2 (a-d) to jp3 (a-d) configure the op amp buffers as inverting or noninverting. surface mount pads are available on the board for 1206 size applicatio n s i n for m atio n wu u u surface mount resistors. the printed circuit layout of dc104 is arranged so that most of the resistor connec- tions for one 8th order filter or two 4th order filters are available on the board. a resistor makes a connection between two filter nodes on the board and for most filter designs, no wiring is required. dc104 component side silkscreen dc104 component side dc104 solder side
15 ltc1068 series applicatio n s i n for m atio n wu u u dc104 schematic inv b hpb/nb bpb lpb sb nc agnd v + nc sa lpa bpa hpa/na inv a 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 inv c hpc/nc bpc lpc sc v nc clk nc sd lpd bpd hpd/nd inv d u1 r22 r l5 r64 r h4 r b4 r l4 r b5 r h5 r h1 r b1 r l1 r g2 c o2 r32 r42 r21 r11 r i1 c i1 jp1 v v + v + v dual supply e1 v in2 e3 v in1 c5 10 m f single supply 1 3 2 e13 clk e4 sgnd e10 sgnd e2 sgnd e12 fgnd r61 r31 r41 r24 r43 r33 r23 r h2 r12 r63 r53 r51 r b2 r l2 r h3 bold line indicates fgnd r l3 r b3 r34 r44 r7 200 w r62 r52 1 3 2 jpc lpc fgnd 13 2 jpb lpb fgnd 1 3 2 jpd lpd fgnd r54 + 273 2 8 u2a 4 1 v + v v c3 0.1 m f e5 v out2 buffer 2 e6 sgnd jp2b 36 jp2c 45 jp2d 18 jp2a c4 0.1 m f c2 0.1 m f r g1 c o1 + 27 5 6 u2b 7 1068 ta03 e7 v out1 buffer 1 e8 sgnd jp3b 36 jp3c 45 jp3d 18 jp3a 1 3 2 jpa lpd fgnd c1 0.1 m f e9 v + e11 v c6 10 m f 16v c7 10 m f 16v buffers configuration assembled as noninverting buffer dual supply inverting buffer dual supply noninverting buffer single supply for noninverting buffer single supply r g2 short res short res jp2a open short open short u2a jp2b short open short open jp2c open open open short jp2d open short open open r g1 short res short res jp3a open short open short u2a jp3b short open short open jp3c open open open short jp3d open short open open demo board dc104b-a dc104b-b dc104b-c dc104b-d u1 ltc1068cg ltc1068cg-200 ltc1068cg-25 ltc1068cg-50 u2 lt1211 lt1211 lt1213 lt1498
16 ltc1068 series applicatio n s i n for m atio n wu u u a surface mount printed circuit layout a very compact surface mount printed circuit layout can be designed with 0603 size surface mount resistors, capacitors and a 28-pin ssop of the ltc1068 product family. an example of a printed circuit layout is shown in the folowing figures for an 8th order elliptic bandpass filter. the total board area of this 8th order filter is 1" by 0.8". no attempt was made to design the smallest possible printed circuit layout. inv b inv c 28 1 hpb/nb hpc/nc 27 2 sb nc nc sc 24 5 r21 4.99k r22 4.99k bpb bpc 26 3 r31 24.9k r32 107k lpa lpd 20 9 r43 43.2k r44 17.4k bpa bpd 19 10 r33 59k r34 63.4k hpa/na hpd/nd 18 11 inv a inv d 17 16 15 12 13 14 r23 4.99k r24 7.5k lpb lpc 25 4 r41 20.5k r51 4.99k r h2 11.3k r11 29.4k v in r64 10k r62 56.2k r h1 28k r h3 15.4k v out agnd v 23 6 v + 22 7 sa sd nc nc clk 21 8 5v ?v 1.75mhz 1068 ta07a u1 ltc1068-25 c1 0.1 f c2 0.1 f r54 4.99k r52 4.99k r l3 45.3k r61 11.3k r l2 23.2k 70khz elliptic bandpass filter, f center = f clk /25 (maximum f center is 80khz, v s = 5v) frequency (khz) 20 gain (db) 10 0 10 20 30 40 50 60 70 80 ?0 40 60 70 1068 ta07b 30 50 80 90 100 gain vs frequency filtercad custom inputs for f c = 70khz 2nd order section f o (khz) q f n (khz) type mode b 67.7624 5.7236 58.3011 hpn 2b c 67.0851 20.5500 81.6810 lpn 1bn a 73.9324 15.1339 81.0295 lpn 2n d 73.3547 16.3491 bp 2b
17 ltc1068 series applicatio n s i n for m atio n wu u u r61 r41 r43 r33 r23 r31 r21 r11 r22 r32 r52 r62 r64 r54 r24 r h3 r h2 r l3 r l2 r34 r44 r h1 r51 gnd gnd v in v out v + v r11 r22 u1 r32 r52 r62 r64 r54 r h1 r21 r51 r61 r43 r24 1068 ta08 r34 r44 c2 c1 r33 r23 r h2 r l3 r l2 r h3 r31 r41 surface mount components (board area = 1" 0.8") component side solder side 1068 ta09 1068 ta10
18 ltc1068 series typical applicatio n s u inv b hpb/nb bpb lpb sb nc agnd v + nc sa lpa bpa hpa/na inv a 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 inv c hpc/nc bpc lpc sc v nc clk nc sd lpd bpd hpd/nd inv d LTC1068-200 r l1 23.2k r l2 14.3k r21 12.4k r22 15.4k r32 10k r52 5.11k r34 10k r24 15.4k r54 5.11k r64 9.09k r62 9.09k r31 10k r11 14.3k r41 15.4k r23 10k r33 12.4k r43 12.4k r b3 23.2k r l3 23.2k 0.1 m f 5v ?v 400khz v out 1068 ta11a 0.1 m f v in frequency (hz) 0.1 ?0 gain (db) group delay (sec) ?0 ?0 ?0 ?0 110 1068 ta11b 10 ?0 ?0 ?0 ?0 0 0 0.2 0.4 0.6 0.8 1.0 0.1 0.3 0.5 0.7 0.9 gain group delay gain and group delay vs frequency LTC1068-200 8th order linear phase lowpass, f cutoff = f clk /400 for ultralow frequency applications filtercad custom inputs for f c = 1hz 2nd order section f o (hz) q q n type mode b 1.7947 0.7347 lp 3 c 1.6002 0.5195 lp 1b a 1.7961 1.1369 1.0159 lpbp 3s d 1.6070 0.5217 lp 1b
19 ltc1068 series typical applicatio n s u inv b hpb/nb bpb lpb sb nc agnd v + nc sa lpa bpa hpa/na inv a 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 inv c hpc/nc bpc lpc sc v nc clk nc sd lpd bpd hpd/nd inv d ltc1068-50 r b1 13.3k r h2 34k r l2 9.09k r a1 56.2k r21 20.5k r22 43.2k r32 43.2k r42 196k r34 14.3k r44 34.8k r24 16.9k r31 10k r11 22.6k r41 22.6k r23 10.7k r33 12.7k r43 48.7k r b3 24.9k r l3 26.7k 0.1 m f 1 m f 3.3v 500khz v out 1068 ta12a v in ltc1068-50 8th order linear phase lowpass, f cutoff = f clk /50 for single supply low power applictions. maximum f cutoff is 20khz with a 3.3v supply and 40khz with a 5v supply frequency (khz) 1 gain (db) group delay ( m s) ?0 ?0 ?0 ?0 10 100 1068 ta12b 10 ?0 ?0 ?0 ?0 0 60 80 100 130 150 70 90 110 120 140 gain group delay gain and group delay vs frequency filtercad custom inputs for f c = 10khz 2nd order section f o (khz) q f n (khz) q n type mode b 9.5241 0.5248 0.5248 ap 4a3 c 11.0472 1.1258 21.7724 lpn 2n a 11.0441 1.3392 1.5781 lpbp 2s d 6.9687 0.6082 lp 3
20 ltc1068 series typical applicatio n s u ltc1068-25 8th order lowpass, f cutoff = f clk /32, attenuation C 50db at (1.25)(f cutoff )and C 60db at (1.5)(f cutoff ). maximum f cutoff = 120khz inv b inv c 28 1 hpb/nb hpc/nc 27 2 sb nc nc sc 24 5 r21 10k r22 10k bpb bpc 26 3 r31 10k r32 32.4k lpa lpd 20 9 r63 8.45k bpa bpd 19 10 r33 118k r34 15k hpa/na hpd/nd 18 11 inv a inv d 17 16 15 12 13 14 r23 10k r24 10k lpb lpc 25 4 r51 4.99k r h2 36.5k r11 32.4k v in r64 3.16k r62 5.9k r h1 18.2k r l1 26.7k r h3 53.6k v out agnd v 23 6 v + 22 7 sa sd nc nc clk 21 8 5v ?v 3.2mhz 1068 ta13a ltc1068-25 0.1 f 0.1 f r53 4.99k r54 4.99k r52 4.99k r l3 20.5k r61 2.21k r l2 40.2k frequency (khz) 20 ?0 gain (db) ?0 ?0 ?0 100 500 1069 ta13b 10 ?0 ?0 ?0 ?0 0 gain vs frequency filtercad custom inputs for f c = 100khz 2nd order section f o (khz) q f n (khz) type mode b 70.9153 0.5540 127.2678 lpn 1bn c 94.2154 2.3848 154.1187 lpn 1bn a 101.4936 9.3564 230.5192 lpn 1bn d 79.7030 0.9340 lp 1b
21 ltc1068 series typical applicatio n s u ltc1068 8th order linear phase bandpass, f center = f clk /128, passband C 3db at (0.88)(f center ) and (1.12)(f center ). maximum f center = 40khz with 5v supplies inv b inv c 24 1 hpb/nb hpc/nc 23 2 sb sc 20 5 r21 4.99k r22 4.99k bpb bpc 22 3 r31 19.6k r41 12.1k r32 21.5k lpa lpd 16 9 r43 10.7k bpa bpd 15 10 r33 14.7k hpa/na hpd/nd 14 11 inv a inv d 13 12 r23 4.99k r34 28.7k r24 4.99k lpb lpc 21 4 r11 26.1k v in r l1 63.4k r h1 7.5k r b2 16.2k r h3 40.2k agnd v 19 6 v + clk 18 7 sa sd 17 8 5v ?v 1.28mhz 1068 ta14a ltc1068 r52 4.99k r54 4.99k 0.1 f 0.1 f r62 7.5k r64 17.8k r l3 14.7k v out frequency (khz) 1 gain(db) 10 0 10 20 30 40 50 60 70 80 ?0 10 100 1068 ta14b gain vs frequency filtercad custom inputs for f c = 10khz 2nd order section f o (khz) q f n (khz) type mode b 8.2199 2.6702 4.4025 hpn 3a c 9.9188 3.3388 bp 1b a 8.7411 2.1125 21.1672 lpn 3a d 11.3122 5.0830 bp 1b 24-lead package
22 ltc1068 series typical applicatio n s u ltc1068 8th order linear phase bandpass, f center = f clk /100, passband C 3db at (0.88)(f center ) and (1.12)(f center ). maximum f center = 50khz with 5v supplies gain vs frequency inv b inv c 24 1 hpb/nb hpc/nc 23 2 sb sc 20 5 r21 10k r22 10k bpb bpc 22 3 r31 25.5k r32 32.4k lpa lpd 16 9 r43 16.9k r63 2.32k r44 12.1k bpa bpd 15 10 r33 17.4k r34 19.1k hpa/na hpd/nd 14 11 inv a inv d 13 12 r23 7.32k r24 10k lpb lpc 21 4 r41 107k r42 26.1k r11 24.3k v in r l1 24.9k r b2 14.3k r h1 51.1k r b3 18.7k v out agnd v 19 6 v + f clk 18 7 sa sd 17 8 5v ?v 1mhz 1068 ta15a ltc1068 0.1 f 0.1 f r53 4.99k frequency (khz) 1 gain(db) 10 0 10 20 30 40 50 60 70 80 ?0 10 100 1068 ta15b filtercad custom inputs for f c = 10khz 2nd order section f o (khz) q f n (khz) type mode b 10.4569 2.6999 17.4706 lpn 2n c 11.7607 3.9841 bp 2 a 8.6632 2.1384 bp 2b d 9.0909 1.8356 bp 3 24-lead package
23 ltc1068 series typical applicatio n s u gain vs frequency inv b inv c 24 1 hpb/nb hpc/nc 23 2 sb sc 20 5 r21 14.7k r22 18.2k bpb bpc 22 3 r31 10k r32 10k lpa lpd 16 9 r43 21.5k r44 10k bpa bpd 15 10 r33 11.3k r34 17.8k hpa/na hpd/nd 14 11 inv a inv d 13 12 r23 21k r24 15.4k lpb lpc 21 4 r41 14.3k r42 18.7k r11 11k v in r l1 348k r l2 10k r h2 200k r h1 11k r h3 95.3k r l3 12.4k v out agnd v 19 6 v + f clk 18 7 sa sd 17 8 5v ?v 1mhz ltc1068 0.1 f 0.1 f 1068 ta16a frequency (khz) 1 gain(db) 10 0 10 20 30 40 50 60 70 80 ?0 10 100 1068 ta16b filtercad custom inputs for f c = 10khz 2nd order section f o (khz) q f n (khz) q n type mode b 10.1389 0.7087 1.7779 hpn 3a c 9.8654 0.5540 44.7214 lpn 3a a 9.8830 0.5434 27.7227 lpn 3a d 12.4097 1.5264 bp 3 24-lead package ltc1068 8th order linear phase bandpass, f center = f clk /100, passband C 3db at (0.7)(f center ) and (1.3)(f center ), superior sinewave burst response, maximum f center = 60khz with 5v supplies
24 ltc1068 series typical applicatio n s u inv b inv c 28 1 hpb/nb hpc/nc 27 2 sb nc nc sc 24 5 r21 10k r22 11.3k bpb bpc 26 3 r31 30.1k r41 10.7k r32 29.4k r42 10k lpa lpd 20 9 bpa bpd 19 10 r33 26.7k r43 12.1k r34 28k r44 22.1k hpa/na hpd/nd 18 11 inv a inv d 17 16 15 12 13 14 r23 10k r24 10k lpb lpc 25 4 r51 4.99k r h2 84.5k r11 36.5k v in r h1 18.2k r h3 47.5k v out agnd v 23 6 v + 22 7 sa sd nc nc clk 21 8 5v 400khz 1068 ta17a ltc1068-50 0.1 f 1 f r l3 15.8k r61 1.74k r l2 17.8k frequency (khz) 26 4 ?0 gain (db) ?0 ?0 ?0 ?0 14 18 22 10 1068 ta17b ?0 10 12 828 26 24 20 16 ?0 ?0 0 gain vs frequency ltc1068-50 8th order linear phase bandpass, f center = f clk /40, passband C 3db at (0.8)(f center ) and (1.2)(f center ) for single supply low power applicaions. maximum f center = 25khz with a single 5v supply filtercad custom inputs for f c = 10khz 2nd order section f o (khz) q f n (khz) type mode b 8.7384 4.0091 4.0678 hpn 2b c 11.6756 4.6752 19.1786 lpn 2n a 10.8117 4.2066 16.0127 lpn 2n d 9.6415 3.6831 bp 2
25 ltc1068 series typical applicatio n s u ltc1068-25 8th order bandpass, f center = f clk /32, passband C 3db at (0.965)(f center ) and (1.35)(f center ). maximum f center = 80khz with 5v supplies inv b inv c 28 1 hpb/nb hpc/nc 27 2 sb nc nc sc 24 5 r21 4.99k r22 4.99k bpb bpc 26 3 r31 97.6k r32 130k lpa lpd 20 9 r63 6.49k bpa bpd 19 10 r33 124k r34 102k hpa/na hpd/nd 18 11 inv a inv d 17 16 15 12 13 14 r23 4.99k r24 4.99k lpb lpc 25 4 r51 4.99k r11 121k v in r64 6.98k r62 9.53k r h1 118k v out agnd v 23 6 v + 22 7 sa sd nc nc clk 21 8 5v ?v 320khz 1068 ta18a ltc1068-25 0.1 f 0.1 f r53 4.99k r54 4.99k r52 4.99k r l3 78.7k r61 8.87k r b2 47.5k frequency (khz) 7.5 gain (db) 10 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 11.5 1068 ta18b 8.5 9.5 10.5 12.5 11 8 9 10 12 gain vs frequency filtercad custom inputs for f c = 10khz 2nd order section f o (khz) q type mode b 10.2398 15.6469 bp 1b c 10.3699 21.1060 bp 1b a 9.6241 18.6841 lp 1b d 9.7744 15.6092 lp 1b
26 ltc1068 series typical applicatio n s u LTC1068-200 8th order highpass, f center = f clk /200, attenuation C 60db at (0.6)(f center ). maximum f cutoff = 20khz with 5v supplies gain vs frequency inv b inv c 28 1 hpb/nb hpb/nc 27 2 sb nc nc sc 24 5 r21 10k r22 21.5k bpb bpc 26 3 r31 16.5k r41 11.3k r32 10.2k r42 18.7k lpa lpd 20 9 bpa bpd 19 10 r33 36.5k r43 20.5k r53 4.99k r63 2.55k r34 14.3k r44 21k hpa/na hpd 18 11 inv a inv d 17 16 15 12 13 14 r23 10k r24 20.5k lpb lpc 25 4 r h2 20.5k r11 18.2k v in r h1 11.8k r l1 66.5k r h3 10k c23 [1/(2 p ?r23 ?c23) = (160)(f cutoff )] v out agnd v 23 6 v + 22 7 sa sd nc nc clk 21 8 5v 200khz ?v 1068 ta19a LTC1068-200 0.1 f 0.1 f r l2 249k frequency (khz) 0.2 ?0 ?0 ?0 ?0 ?0 gain (db) ?0 ?0 ?0 0 110 1068ta19b 10 filtercad custom inputs for f c = 1khz 2nd order section f o (khz) q f n (khz) type mode b 0.9407 1.5964 0.4212 hpn 3a c 1.0723 0.5156 0.2869 hpn 3a a 0.9088 3.4293 0.5815 hpn 2b d 0.9880 0.7001 0.0000 hp 3
27 ltc1068 series dimensions in inches (millimeters) unless otherwise noted. package descriptio n u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. n24 1197 0.255 0.015* (6.477 0.381) 1.265* (32.131) max 12 3 4 5 6 7 8910 19 11 12 13 14 16 15 17 18 20 21 22 23 24 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) g28 ssop 0694 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 14 13 0.397 ?0.407* (10.07 ?10.33) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** n package 24-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510)
28 ltc1068 series 1068fa lt/tp 0998 2k rev a ? printed in usa typical applicatio n u linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com LTC1068-200 8th order notch, f notch = f clk /256, f C 3db at (0.9) (f notch ) and (1.05)(f notch ), attenuation at f notch greater than 70db for f notch in the frequency range 200hz to 5khz inv b inv c 28 1 hpb/nb hpb/nc 27 2 sb nc nc sc 24 5 r21 5.11k r22 6.34k bpb bpc 26 3 r31 51.1k r41 100k r32 84.3k lpa lpd 20 9 r63 8.06k bpa bpd 19 10 r43 178k c23 470pf r34 75k hpa/na hpd 18 11 inv a inv d 17 16 15 12 13 14 r33 124k r23 10k r24 7.32k r h4 5.11k r l4 475k lpb lpc 25 4 r51 5.11k r h2 5.11k r11 51.1k v in r64 7.87k r g 15k r62 5.76k r l2 66.5k r h1 5.11k r h3 5.11k agnd v 23 6 v + 22 7 sa sd nc nc clk 21 8 5v ?v f clk = (256)(f notch ) v out 1068 ta01 LTC1068-200 0.1 f c21 470pf 0.1 f r53 5.11k r54 5.11k r52 5.11k r61 8.06k c22 470pf + lt1354 ? linear technology corporation 1996 related parts part number description comments ltc1064 universal filter, quad 2nd order 50:1 and 100:1 clock-to-f o ratios, f o to 100khz, v s = up to 7.5v ltc1067/ltc1067-50 low power, dual 2nd order rail-to-rail, v s = 3v to 5v ltc1164 low power universal filter, quad 2nd order 50:1 and 100:1 clock-to-f o ratios, f o to 20khz, v s = up to 7.5v ltc1264 high speed universal filter, quad 2nd order 20:1 clock-to-f o ratio, f o to 200khz, v s = up to 7.5v relative frequency (f in /f notch ) gain (db) ?0 ?0 10 1.1 1068 ta02 ?0 ?0 ?0 ?0 0 ?0 ?0 ?0 0.8 0.9 1.0 1.2 gain vs frequency

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